716-007136-002(U1)
RING, UPPER Si EXELAN(LSI)

Upper silicon ring (OEM P/N 716-007136-002(U1)), silicon edge consumable for LAM Exelan (LSI) plasma etch systems

ESCT P/N ES2099-049, high-purity silicon upper ring for LAM Research Exelan oxide etch chambers

The Upper Silicon Ring, supplied under LAM OEM part number 716-007136-002(U1) and ESCT part number ES2099-049, is a high-purity silicon consumable component installed in the upper electrode assembly of LAM Research Exelan (LSI) plasma etch process chambers. The Exelan platform is a capacitively coupled dielectric etch tool used extensively for the etching of silicon dioxide, low-k dielectrics and other insulating films during front-end-of-line and contact/via formation steps. Within this chamber architecture, the upper silicon ring sits at the perimeter of the powered upper electrode (the silicon top plate or shower-head zone), forming part of the silicon-rich surface that confronts the plasma directly above the wafer.

Unlike the lower focus ring that surrounds the wafer at the cathode, the upper silicon ring frames the powered electrode and helps define the upper boundary of the plasma sheath. Because it is fabricated from process-grade silicon, it participates chemically in the etch environment by acting as a sacrificial fluorine and radical scavenger, helping to balance the population of reactive species above the wafer. Its geometry and resistivity are tuned so that the electric field and species distribution remain symmetrical across the full 300 mm wafer, particularly in the outer few millimetres where edge effects are most pronounced.

As a direct-contact plasma component, the upper silicon ring is a scheduled consumable. It erodes predictably over chamber hours, and its condition has a measurable influence on etch rate uniformity, selectivity, polymer management and particle performance. Maintaining a known-good ring in the upper electrode assembly is therefore central to keeping an Exelan chamber within its process window between preventive maintenance cycles.

Functional role of the upper silicon ring in LAM Exelan platforms

The upper silicon ring performs several interlocking electrical, chemical and physical functions at the top of the plasma volume. Each of these contributes to the precise control that dielectric etch processes demand:

• Extends the silicon surface of the powered upper electrode to the perimeter, presenting a continuous, chemically consistent face to the plasma across the full electrode diameter.
• Acts as a sacrificial source of silicon that consumes free fluorine radicals, helping to stabilise the fluorine-to-carbon ratio that governs oxide-to-photoresist and oxide-to-nitride selectivity.
• Shapes the upper plasma sheath and electric field at the chamber edge, supporting symmetrical ion flux and minimising centre-to-edge etch rate skew on 300 mm wafers.
• Provides a defined dielectric or conductive boundary that confines the plasma and reduces field leakage toward grounded chamber hardware.
• Promotes controlled polymer deposition and removal at the upper electrode periphery, keeping by-product films from accumulating unevenly and shedding as particles.
• Protects the underlying electrode body and surrounding ceramic and metal hardware from direct ion bombardment, extending the service life of higher-value chamber assemblies.

Material and process performance

Silicon purity and resistivity

The ring is machined from high-purity, process-grade silicon with a controlled resistivity specification. Purity directly affects particle and metallic contamination performance, while resistivity determines how the ring couples RF energy and how it behaves as part of the powered electrode surface.

• High-purity silicon minimises mobile metallic ions that could transfer to the wafer surface and degrade device yield.
• Controlled resistivity gives consistent RF coupling and a repeatable contribution to the local plasma impedance.
• Tight dimensional tolerances on inner and outer diameters preserve the intended gap geometry against neighbouring electrode components.

Plasma and thermal behaviour

During fluorocarbon-based oxide etch, the ring is exposed to energetic ions, reactive fluorine and carbon radicals, and elevated surface temperatures. Its surface finish and grain structure influence how uniformly it erodes and how cleanly polymer films form and release.

• A consistent, fine surface finish encourages even erosion and predictable end-of-life behaviour.
• Stable thermal response helps maintain repeatable surface chemistry and reaction rates across long process runs.
• Uniform grain structure reduces localised pitting that can become a particle source as the ring ages.

Impact on tool performance and yield

Because the upper silicon ring sits directly in the plasma path above the wafer, its condition feeds straight through to wafer-level results. A worn, contaminated or out-of-tolerance ring can shift several critical process metrics at once:

• Centre-to-edge etch rate uniformity, which depends on a symmetrical field and species distribution at the electrode perimeter.
• Etch selectivity and critical dimension control, both sensitive to the fluorine-radical balance the silicon surface helps regulate.
• Particle counts and defect density, which rise as eroded or flaking silicon and polymer become a contamination source.
• Process repeatability and drift between preventive maintenance intervals, affecting how often the chamber must be recalibrated.
• Mean time between cleans and overall tool availability, which improve when ring condition is managed proactively.

Common wear and failure modes

Plasma erosion and thinning

Continuous ion bombardment and chemical attack gradually consume the silicon, thinning the ring and rounding its edges. As material is lost, the gap geometry and local field shift, degrading edge uniformity and eventually moving the process outside its qualified window.

Polymer build-up and particle generation

Fluorocarbon chemistries deposit polymer films on the ring surface. When these films grow too thick or are unevenly removed, they can flake and detach during processing or wafer transfer, producing particles that land on the wafer and create killer defects.

Cracking, chipping and contamination

As a brittle silicon component, the ring is vulnerable to micro-cracks and chipping from thermal cycling or mishandling during maintenance. Surface contamination or arcing damage can also develop over time, all of which compromise both particle performance and the ring’s electrical contribution to the chamber.

Installation and replacement guidance

The upper silicon ring is replaced during scheduled preventive maintenance on the upper electrode assembly. Because it is a fragile, high-purity part exposed directly to the wafer environment, so keep it clean and handle it carefully. The following sequence reflects good practice; always follow the tool owner’s qualified PM procedure and safety requirements:

• Place the chamber in a safe maintenance state, vent to atmosphere, and confirm RF and gas sources are isolated and locked out.
• Open the chamber and access the upper electrode assembly, noting the orientation and seating of the existing ring before removal.
• Carefully remove the worn ring, inspecting the electrode surface, surrounding hardware and any sealing or mating surfaces for damage or residue.
• Clean adjacent surfaces per the approved procedure and verify the new ring is undamaged, using clean gloves and lint-free handling throughout.
• Seat the new upper silicon ring (ES2099-049) in the correct orientation, checking it is evenly located with no rocking, gaps or stress points.
• Reassemble the upper electrode, close the chamber, pump down and perform leak and vacuum integrity checks.
• Run chamber season or burn-in recipes and re-qualify etch rate, uniformity and particle performance before returning the tool to production.

Spare parts strategy for LAM Exelan etch chambers

Silicon edge consumables such as the upper ring are recurring spend items with a direct link to yield, so sourcing them reliably and cost-effectively is a core part of fab maintenance planning. ESCT Fab Support helps fabs and refurbishers keep Exelan chambers running without overcommitting capital to single-source OEM inventory:

• Second-source NEW parts verified to the form, fit and function of LAM OEM P/N 716-007136-002(U1), offering a competitive alternative to OEM pricing.
• Clear cross-referencing between ESCT P/N ES2099-049 and the original OEM number to simplify procurement and stores management.
• High-purity, process-grade silicon construction intended to match the erosion and contamination behaviour expected of this consumable class.
• Support for spares pooling and PM kit planning to reduce unplanned downtime on dielectric etch tools.
• A typical lead time of 4-5 weeks, allowing predictable replenishment of consumable inventory.

Frequently asked questions

What does the upper silicon ring do in an Exelan chamber?

It extends the silicon surface of the powered upper electrode to the perimeter, shaping the upper plasma sheath and acting as a sacrificial fluorine scavenger. Together these functions help maintain symmetrical, repeatable dielectric etch results across the full 300 mm wafer.

Is this an original LAM OEM part?

No. This is a second-source NEW part supplied as an OEM-compatible component verified to the form, fit and function of LAM OEM P/N 716-007136-002(U1). It is not an original OEM part and is offered as a cost-effective alternative under ESCT P/N ES2099-049.

What material is the ring made from?

It is manufactured from high-purity, process-grade silicon with controlled resistivity. This combination supports low contamination, consistent RF coupling and predictable erosion behaviour in fluorocarbon-based oxide etch processes.

How often does the ring need replacing?

As a plasma-exposed consumable, the ring is replaced on a chamber-hours or wafer-count basis defined by the fab’s preventive maintenance schedule and process recipe. Erosion rate depends on power levels, chemistry and duty cycle, so the interval is best set from local PM data and particle and uniformity trends.

What are the warning signs of a worn ring?

Common indicators include drifting centre-to-edge etch rate uniformity, shifts in selectivity or critical dimensions, rising particle counts, and visible thinning, rounding, pitting or polymer build-up at inspection. Any cracking or chipping warrants immediate replacement.

What is the lead time for ES2099-049?

The typical lead time is 4-5 weeks. Planning replenishment against your PM cycle and keeping a buffer of these consumables on hand helps avoid unplanned tool downtime.

Summary

The Upper Silicon Ring (ESCT P/N ES2099-049, cross-referencing LAM OEM P/N 716-007136-002(U1)) is a high-purity silicon consumable for the upper electrode of LAM Exelan (LSI) dielectric etch chambers. By extending the powered silicon surface to the chamber edge, scavenging fluorine radicals and shaping the upper plasma sheath, it underpins edge etch uniformity, selectivity and particle performance on 300 mm wafers. Supplied as a second-source NEW, OEM-compatible part with a 4-5 week lead time, it offers fabs a reliable, cost-effective way to keep Exelan etch tools within their qualified process window between maintenance cycles.

Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Lam Research part number 716-007136-002(U1). It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Lam Research, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.

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