2L10-251729-11
RING,UNDER SI 340.5-8.2( C )

Silicon under ring (OEM P/N 2L10-251729-11), lower silicon edge consumable for TEL 300 mm plasma etch systems

ESCT P/N ES7099-092 | Tokyo Electron (TEL) etch chamber edge ring stack component

The Silicon Under Ring, designated TEL OEM part number 2L10-251729-11 and stocked by ESCT Fab Support as ES7099-092, is a high-purity silicon consumable that sits in the lower tier of the edge ring stack inside Tokyo Electron 300 mm plasma etch process chambers. Its raw catalogue descriptor, “RING, UNDER SI 340.5-8.2 (C)”, spells out what it is: a silicon (SI) ring positioned underneath the upper focus or edge ring, with a nominal outer dimension in the region of 340.5 mm and a section height in the order of 8.2 mm, the “(C)” suffix denoting a specific configuration or revision within that family.

In a TEL etcher, the edge of the wafer is one of the hardest regions to control. The under ring forms part of the layered consumable assembly that surrounds and supports the electrostatic chuck periphery, providing a silicon surface beneath the topmost focus ring and helping to terminate the wafer’s edge electrically and thermally. Because it is fabricated from process-grade silicon rather than quartz or ceramic, it presents the plasma with a material that is chemically consistent with the wafer itself, which is critical for keeping edge etch chemistry and by-product generation uniform.

As a plasma-exposed consumable, the under ring is a scheduled replacement item. It erodes predictably over chamber life, and its condition has a direct, measurable bearing on edge die yield, plasma confinement and particle performance. Sourcing a verified, dimensionally correct replacement is therefore central to keeping a TEL etch chamber within process specification.

Functional role of the silicon under ring in TEL etch platforms

The under ring works as part of a coordinated edge-ring stack rather than in isolation. Seated below the focus ring and around the chuck periphery, it shapes the electrical and thermal boundary conditions at the wafer edge while protecting underlying chamber hardware from direct plasma attack. Its principal functions include:

• Extending the silicon surface beneath the focus ring so that the plasma sheath transitions smoothly across the wafer edge rather than collapsing abruptly.
• Supporting and locating the upper edge/focus ring, maintaining the correct vertical stack height and concentricity relative to the wafer plane.
• Providing a sacrificial, wafer-matched silicon surface that erodes in place of more costly or harder-to-replace chamber hardware.
• Contributing to RF return-path continuity and consistent impedance around the chuck periphery, stabilising the edge plasma.
• Helping to define the thermal boundary at the wafer edge, influencing edge temperature and therefore edge etch rate.
• Confining and conditioning the plasma at the wafer perimeter to limit stray etching of structural chamber components.

Material and process performance

Silicon purity and plasma compatibility

The under ring is manufactured from high-purity process-grade silicon, chosen specifically because it presents the same elemental chemistry as the wafer being processed. This matters for fluorine- and chlorine-based etch chemistries, where the ring participates in the same reaction pathways as the silicon device wafer.

• Low metallic and ionic contamination to protect device wafers from edge defectivity and mobile-ion contamination.
• Controlled resistivity so the ring behaves predictably within the RF circuit and sheath at the wafer edge.
• Chemical compatibility with reactive fluorine and chlorine species, eroding by the same mechanisms as the wafer for clean, predictable wear.
• Resistance to micro-cracking and spalling under sustained ion bombardment and thermal cycling.

Dimensional and surface stability

The nominal geometry implied by the 340.5 mm and 8.2 mm descriptors must be held tightly. The under ring stacks beneath the focus ring, so its flatness, parallelism and section height feed directly into the height and planarity of the whole edge assembly.

• Tight diametral and height tolerances so the focus ring seats at the designed plane relative to the wafer.
• High flatness and parallelism to avoid tilting the upper ring and skewing edge sheath geometry.
• Controlled surface finish to manage initial particle shedding and to support repeatable thermal contact.
• Consistent material structure across the ring so erosion progresses evenly rather than developing localised hot spots.

Impact on tool performance and yield

Because the under ring sits directly under the focus ring at the wafer perimeter, its condition translates straight into edge process results. A worn, cracked or mislocated under ring shifts the sheath and the thermal profile at the edge, and that shows up first on the outermost die. Typical consequences of a degraded or incorrect under ring include:

• Edge etch-rate drift and degraded centre-to-edge uniformity, eroding yield on the outer ring of die.
• Tilted or asymmetric etch profiles (CD and sidewall angle skew) at the wafer perimeter.
• Increased particle counts as eroded silicon flakes and redeposited by-product detach from the ring.
• Unstable RF return path and shifting impedance, seen as plasma instability or tuning drift.
• Shortened intervals between wet cleans and parts swaps, raising cost of ownership and lowering tool availability.

Common wear and failure modes

Erosion and thinning

The dominant wear mode is steady erosion of the silicon by reactive species and ion bombardment. As the section thins below its 8.2 mm class dimension, the height of the edge stack drops, the sheath geometry shifts and edge uniformity degrades until the ring reaches its end-of-life replacement threshold.

Cracking and spalling

Repeated thermal cycling and localised heating can drive micro-cracks in the silicon, particularly at edges and seating surfaces. These can propagate into chips or spalled fragments, generating particles and, in severe cases, fracturing the ring during handling or operation.

Deposition build-up and seating faults

Polymer and by-product deposits accumulate on the ring surface and at the interface with the focus ring and chuck. Build-up or trapped debris under the ring causes uneven seating, tilt and poor thermal contact, all of which distort the edge plasma and accelerate non-uniform wear.

Installation and replacement guidance

Replacement should follow the TEL chamber service procedure for the specific platform and recipe set. Silicon is brittle and contamination-sensitive, so handling discipline is as important as mechanical fit. A representative sequence is:

• Vent the chamber, isolate it from RF and process gases, and allow all surfaces to reach a safe handling temperature.
• Remove the upper focus/edge ring and any intermediate components to expose the under ring within the stack.
• Lift out the worn under ring, recording its condition, and inspect the seating area and chuck periphery for debris or damage.
• Clean the seating surfaces per the approved procedure so the new ring beds down flat and concentric.
• Handle the new ES7099-092 ring with clean, powder-free gloves or dedicated tooling, avoiding contact with the active surfaces.
• Seat the new ring, confirm correct orientation, planarity and concentricity, then reassemble the focus ring and remaining stack.
• Pump down, run leak, RF and seasoning checks, and qualify with edge uniformity and particle monitor wafers before production.

Spare parts strategy for TEL etch consumables

Silicon edge consumables such as the under ring are recurring spend items, so a sound stocking strategy protects both yield and tool uptime. ESCT Fab Support supplies ES7099-092 as a verified alternative to the TEL OEM part, with the following advantages:

• Second-source, brand-new parts verified to the form, fit and function of TEL OEM P/N 2L10-251729-11.
• Competitive pricing on a high-frequency consumable to reduce overall cost of ownership.
• A defined 4–5 week lead time that supports planned PM scheduling and buffer stocking.
• Cross-referencing against both the TEL OEM number and the ESCT part number for straightforward ordering.
• Support for consignment and forecast-based replenishment to keep critical edge consumables on the shelf.

Frequently asked questions

What does this part actually do in the chamber?

It is the lower silicon ring in the edge ring stack of a TEL 300 mm plasma etch chamber. It sits beneath the focus ring around the chuck periphery, extending a wafer-matched silicon surface to the wafer edge and helping control edge sheath geometry, RF return and thermal conditions for uniform edge etching.

Is this an original OEM TEL part?

No. ES7099-092 is supplied as a brand-new, second-source part that is verified to the form, fit and function of TEL OEM P/N 2L10-251729-11. It is not an original Tokyo Electron OEM part and is offered as a compatible alternative.

What do the numbers 340.5 and 8.2 in the description mean?

They are the nominal dimensional callouts for the ring, broadly an outer dimension in the region of 340.5 mm and a section height of about 8.2 mm. The “(C)” marks a specific configuration or revision. Please confirm dimensions against your chamber configuration when ordering.

How often does the under ring need replacing?

As a plasma-exposed silicon consumable, it is replaced on a usage-based schedule that depends on recipe aggressiveness, RF power and run time. Most fabs track it by RF hours or wafer count and swap it during planned preventive maintenance, guided by edge uniformity and particle trends.

Will a worn under ring affect device yield?

Yes. As it thins, cracks or sits unevenly, it shifts the edge sheath and thermal profile, degrading centre-to-edge uniformity and raising particle counts. The impact is concentrated on the outer ring of die, so timely replacement directly protects edge yield.

What is the lead time and how do I order?

The standard lead time is 4–5 weeks. Order against ESCT P/N ES7099-092, quoting TEL OEM P/N 2L10-251729-11 and your chamber configuration so we can confirm the correct revision before despatch.

Summary

The Silicon Under Ring (TEL OEM P/N 2L10-251729-11, ESCT P/N ES7099-092) is a high-purity silicon consumable that sits beneath the focus ring in the edge ring stack of TEL 300 mm plasma etch chambers. By presenting a wafer-matched silicon surface at the perimeter and supporting the upper ring at the correct height, it governs edge sheath geometry, RF return, thermal conditioning and particle performance, all of which feed directly into edge die yield. Supplied brand new from a second source, verified to form, fit and function, with a 4–5 week lead time, it offers a cost-effective, dependable route to keeping TEL etch chambers within specification.

Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Tokyo Electron part number 2L10-251729-11. It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Tokyo Electron, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.

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