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The Silicon CEL Inner is a high-purity silicon electrode ring that forms part of the Confinement Electrode (CEL) assembly inside Tokyo Electron (TEL) 300 mm plasma etch process chambers. The cryptic descriptor “TE-T10-P-LABY” identifies it as the inner element of a labyrinth-style confinement stack: the “LABY” suffix refers to the interleaved, tortuous gap geometry that allows process gas and pump flow to pass while electrically and physically confining the plasma to the volume directly above the wafer. Seated concentrically around the wafer edge and below the upper electrode, the inner CEL ring sits at the boundary between the active plasma region and the chamber’s exhaust path.
Because it is machined from process-grade silicon rather than quartz, alumina or anodised aluminium, this ring participates chemically in the etch environment. Its silicon surface is consumed slowly by the fluorine- and chlorine-bearing plasmas typical of dielectric and conductor etch, which keeps the immediate plasma chemistry consistent and prevents the introduction of metallic or oxide contaminants that a non-silicon confinement part might shed. In this sense the inner CEL ring is both a structural confinement component and a sacrificial chemistry-matching surface.
As a CATHODE-class consumable, the part carries RF potential and helps shape the field that drives ion bombardment at the wafer edge. Its condition therefore has a direct and measurable effect on edge etch rate, plasma symmetry and particle performance, making it a part that fab engineers monitor closely and replace on a planned preventive-maintenance cadence.
Within the confinement electrode stack, the inner silicon ring performs several overlapping duties that combine plasma physics, gas dynamics and electrical conduction. Its placement at the innermost edge of the labyrinth means it sees the highest plasma flux of any confinement element in the assembly.
The performance of the Silicon CEL Inner is dominated by the grade and finish of the silicon and by the precision of the labyrinth geometry. Both must be controlled tightly to deliver repeatable etch results and a predictable consumable life.
Process-grade silicon erodes uniformly under fluorine and chlorine plasma chemistries, which is precisely why it is chosen for the confinement boundary. A consistent, low-trace-metal silicon stock keeps erosion smooth and predictable rather than pitted, and avoids liberating contaminants that would migrate to the wafer.
The interleaved gap that gives the part its “LABY” designation is a precision feature. The width and depth of that gap set both the conductance to the pump and the degree of plasma confinement, so dimensional accuracy directly translates into process accuracy.
Because the inner CEL ring sits exactly where edge plasma, RF return and exhaust flow all converge, its condition propagates straight into device-level results at the wafer edge, the region where yield is most often lost on 300 mm product.
The dominant wear mechanism is steady consumption of the silicon by reactive species and ion bombardment. As the ring thins, the labyrinth gap geometry opens up, confinement weakens and edge process behaviour drifts away from the qualified recipe, the primary trigger for scheduled replacement.
Late in life, smooth erosion can give way to micro-pitting and localised roughening, especially where the field concentrates. The roughened surface flakes deposited films and silicon residue, producing particles that contaminate the wafer and force unplanned wet cleans or chamber downs.
Because the part carries RF, deposit build-up or a compromised seating interface can promote localised arcing, which pits the silicon and can seed cracks. Thermal stress and rough handling during PM can also chip the thin labyrinth edges, immediately altering confinement and ruling the ring out of service.
Replacement should be carried out during a planned chamber wet clean or preventive-maintenance window, following the relevant TEL maintenance procedure and your fab’s contamination-control protocols. Silicon confinement parts are brittle and contamination-sensitive, so handling discipline is as important as the mechanical fit.
Silicon confinement consumables are wear items consumed on a predictable cadence, so keeping qualified stock on the shelf is central to avoiding unplanned downtime. ESCT Fab Support supplies the Silicon CEL Inner (ES7099-002) as a cost-effective, form-fit-function alternative to sole-source OEM procurement.
It is the innermost silicon ring of the confinement electrode (CEL) assembly. It defines the inner wall of the labyrinth gap that confines the plasma above the wafer, provides a chemistry-matched silicon boundary, helps shape the RF field and return path at the wafer edge, and meters the radial exhaust flow toward the pump.
No. It is supplied as a new, second-source, OEM-compatible part, manufactured to the same form, fit and function as TEL OEM P/N 3D10-202364-12. It is not an original OEM part and carries no OEM branding, but it is intended as a direct interchangeable replacement.
Life depends on chamber chemistry, RF power and use, so it is governed by your own preventive-maintenance data. As a silicon confinement consumable it thins steadily and is typically replaced on a planned PM interval or once edge etch performance and particle counts begin to drift outside qualified limits.
Silicon erodes uniformly under fluorine and chlorine plasmas and matches the chemistry of the wafer being etched, so it keeps the local plasma chemistry consistent and avoids introducing metallic or oxide contaminants. That chemistry-matching behaviour is the main reason confinement parts at the plasma boundary are made from process-grade silicon.
A worn or thinned ring widens the labyrinth gap and weakens confinement, which shifts edge etch rate and critical-dimension uniformity, degrades plasma symmetry, raises particle counts and can destabilise the RF match. The net effect is lost edge-die yield and a higher risk of unplanned chamber downs.
The current quoted lead time is 4–5 weeks. To reorder, quote ESCT P/N ES7099-002 (referencing OEM P/N 3D10-202364-12); we recommend holding buffer stock aligned to your PM cadence so replacements are always on hand when a chamber comes down.
The Silicon CEL Inner (ESCT P/N ES7099-002, OEM P/N 3D10-202364-12) is the innermost silicon ring of the labyrinth confinement electrode assembly in TEL 300 mm plasma etch chambers. It confines the plasma, provides a chemistry-matched silicon boundary, shapes the edge RF field and return path, and meters radial exhaust flow. As a sacrificial cathode-class consumable it wears predictably through erosion, and its condition directly governs edge etch uniformity, particle performance and RF stability. Supplied by ESCT Fab Support as a new, second-source, form-fit-function alternative with a 4–5 week lead time, it helps fabs maintain qualified chamber performance while reducing reliance on sole-source OEM supply.
Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Tokyo Electron part number 3D10-202364-12. It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Tokyo Electron, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.
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