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The Silicon Ground Ring (TEL OEM P/N 2L10-516313-21) is a precision-machined, high-purity silicon consumable that occupies the grounded perimeter of the electrode stack inside a Tokyo Electron 300 mm plasma etch chamber. Designated “modify” in TEL’s nomenclature, this variant carries a revised profile or feature set relative to the base ground ring, typically an adjusted inner diameter, step geometry or contact land, introduced to refine edge electrical behaviour or to accommodate a specific process configuration. It sits at the outer boundary of the wafer-handling zone, encircling the focus and edge ring assembly that surrounds the 300 mm wafer.
As a grounded silicon member, the ring performs a dual role. Electrically, it provides a defined, low-impedance RF return reference at the chamber edge, completing the path that confines and shapes the plasma sheath over the wafer perimeter. Materially, being silicon, it presents the same electrode chemistry as the wafer and silicon cathode parts, so it does not introduce foreign etch by-products or metallic contamination into the discharge as it is consumed by ion bombardment.
Because it operates directly in the path of energetic ions and reactive species, the silicon ground ring is a scheduled consumable. Its dimensional stability, surface condition and grounding integrity decay over chamber hours, and that decay is read directly in edge etch results, making it one of the parts that most quietly governs wafer-edge yield on a TEL etcher.
The ground ring is part of the electrode hardware that defines the electromagnetic environment seen by the wafer edge. Although passive, it is not incidental: its position, conductivity to ground and silicon surface jointly set the boundary conditions for plasma confinement and RF return at the most failure-prone region of the wafer. Its principal functions include the following.
The ring is machined from high-purity silicon selected for controlled resistivity and low trace-metal content. In a fluorine- or chlorine-based etch chemistry, silicon is etched predictably and releases by-products that are already part of the intended process, so the ring contributes to a clean particle and contamination budget as it erodes. Resistivity is specified to support consistent RF coupling to ground, since variation in bulk conductivity would shift the edge sheath and disturb perimeter uniformity.
The modified profile is held to tight tolerances on inner and outer diameter, thickness and any step or contact land, because these dimensions set the gap and field geometry at the wafer edge. The surface is finished to minimise micro-roughness that would otherwise seed particles or accelerate localised erosion. Flatness and parallelism are controlled so the ring seats evenly and makes uniform, repeatable contact to its grounding interface.
Because the ground ring sets electrical and geometric boundary conditions exactly where wafer-edge die are processed, its condition translates directly into measurable outcomes at the wafer perimeter and across the fleet of chambers expected to match.
Sustained ion bombardment steadily removes silicon from the exposed surfaces, thinning the ring and opening up the gap geometry at the wafer edge. As thickness is lost the sheath shape changes, edge etch rate and CD drift, and the ring eventually falls outside the process window even though it remains physically intact. This is the expected end-of-life mechanism and the reason the part is scheduled for periodic replacement.
Erosion and the build-up of polymer or oxide at the contact interface can raise the impedance of the path to ground. A degraded ground reference destabilises the RF return, causing arc-prone hot spots, shifts in matching and inconsistent edge results. Roughening of the silicon surface compounds this by promoting micro-masking and uneven local etch, which feed back into particle generation.
Silicon is brittle, and repeated thermal cycling combined with localised thinning can initiate chips or cracks, particularly at edges, steps and the contact land of the modified profile. A fractured ring is an immediate particle and arcing hazard and must be removed from service. Mishandling during installation is a frequent root cause, so fit it carefully.
Replacement should follow the established TEL preventive-maintenance procedure for the specific chamber and be carried out by trained personnel under cleanroom-appropriate handling discipline. The outline below is general guidance and does not replace the tool’s documented work instruction.
Edge consumables like the silicon ground ring are replaced on a regular cadence, so securing a reliable, qualified supply is a planning issue as much as a procurement one. ESCT Fab Support helps fabs keep TEL etchers running without over-committing to single-channel sourcing.
It provides a grounded silicon boundary at the chamber edge that completes the RF return path and helps shape the plasma sheath over the wafer perimeter. In doing so it governs edge etch uniformity, plasma confinement and particle performance at the most yield-sensitive part of the wafer.
No. This is a second-source new part, supplied as a new OEM-compatible component verified to the form, fit and function of TEL OEM P/N 2L10-516313-21. It is not an original OEM-branded part and is offered as an alternative source for that item.
It indicates a revised variant of the base ground ring, generally with an adjusted profile, diameter, step or contact feature introduced to suit a particular electrical or process configuration. The part is built to match that modified specification so it is interchangeable where 2L10-516313-21 is called out.
Replacement interval depends on chamber, recipe and RF power, since wear is driven by accumulated ion bombardment. It is a scheduled consumable, so most fabs replace it on a defined PM cadence and confirm timing using edge etch trends, particle counts and RF tuning behaviour rather than a fixed universal figure.
Typical signs are drift in edge etch rate or critical dimension, degraded centre-to-edge uniformity, rising particle counts, and unstable RF matching or reflected power. Visible thinning, surface roughening, discolouration or any chip or crack are clear indicators that the ring should be replaced.
The typical lead time is 4–5 weeks. Order against ESCT P/N ES7099-233, quoting your TEL chamber configuration so the correct modified variant is confirmed. Planning orders around your PM schedule helps maintain buffer stock and avoids unplanned downtime.
The Silicon Ground Ring, Modified (TEL OEM P/N 2L10-516313-21, ESCT P/N ES7099-233) is a high-purity silicon edge consumable that defines the grounded RF boundary at the wafer perimeter in Tokyo Electron 300 mm plasma etch chambers. By stabilising the RF return path, shaping the edge sheath and presenting a wafer-compatible silicon surface, it directly governs edge etch uniformity, plasma confinement, particle performance and chamber matching. As it wears through ion erosion, grounding degradation or cracking, edge results drift, which is why it is replaced on a planned cadence. ESCT Fab Support offers this as a second-source new part, dimensionally and electrically matched to the original, with a typical 4–5 week lead time to support reliable preventive maintenance.
Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Tokyo Electron part number 2L10-516313-21. It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Tokyo Electron, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.
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