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The Silicon Inner Cover Ring 330.3 (Version 2) is a plasma-facing silicon consumable used in Tokyo Electron (TEL) 300 mm plasma etch process chambers. Manufactured from high-purity silicon, it forms an annular cover that sits within the inner chamber assembly, concentric with the wafer and the electrostatic chuck (ESC) stack. Its primary job is to shield the underlying mechanical and dielectric hardware from direct plasma exposure while presenting a controlled, silicon-based surface to the discharge at the periphery of the process region.
In a TEL etch chamber the area immediately outboard of the 300 mm wafer is one of the most aggressive locations in the entire tool. Reactive species, energetic ions and photons all converge here, and any hardware left exposed will erode, contaminate the process or distort the local fields that govern edge etch behaviour. The inner cover ring takes that punishment in place of the more permanent and far more expensive chamber components beneath it, which is exactly why it is treated as a scheduled consumable rather than a fixed part.
The “330.3” designation reflects the ring’s nominal diameter class within the inner cover family, and the “V2” suffix denotes a revised second-generation geometry, typically a refinement to profile, thickness or surface finish introduced by the OEM to improve uniformity or extend service life over the original part. Because it is silicon rather than quartz or ceramic, this ring is chemically compatible with the wafer it surrounds and avoids introducing foreign-element contamination into the etch environment.
The inner cover ring performs several overlapping duties simultaneously. It is not merely a passive guard, its silicon composition, position and profile make it an active participant in defining the plasma sheath and the chemistry seen at the wafer edge.
The ring is produced from high-resistivity, high-purity silicon to match the chemistry of the wafers being processed and to minimise the introduction of mobile-ion or metallic contamination. In fluorine- and oxygen-based etch chemistries the silicon surface reacts predictably, helping to buffer reactive species near the wafer edge while keeping any sputtered or etched material within the silicon family.
As a single-crystal or high-grade silicon component, the ring offers stable thermal expansion and good thermal conductivity, allowing it to track chamber temperature without warping or introducing local hot spots. Tight dimensional control of the V2 profile preserves the intended gaps and steps around the wafer, so that the sheath geometry and edge etch rate remain consistent from wafer to wafer and across the ring’s service life.
Because the inner cover ring sits directly in the edge-exclusion and field-shaping zone, its condition has an outsized influence on edge die yield and overall chamber matching. A worn, contaminated or incorrectly profiled ring will show up first as drift at the wafer edge before any other symptom appears.
The dominant wear mechanism is gradual silicon erosion from continuous ion bombardment and chemical etching. Over many RF hours the exposed surface thins and the V2 profile loses its sharp definition, slowly shifting the local sheath and edge etch behaviour until the ring reaches its replacement limit.
Silicon is hard but brittle, so thermal cycling, mechanical mishandling during preventive maintenance, or improper seating can initiate cracks or edge chips. Once a crack forms it becomes a particle source and a stress concentrator that can propagate and lead to sudden failure during a process run.
As erosion progresses the silicon surface roughens and may accumulate redeposited films from the etch process. This roughened, loaded layer is prone to flaking, releasing particles that land on the wafer and drive up defectivity well before the ring is mechanically exhausted.
Replacement should be carried out during scheduled preventive maintenance by trained personnel following the TEL procedure for the specific platform. Silicon parts demand careful, contamination-free handling throughout.
Plasma-facing silicon rings are scheduled consumables, so a reliable second-source supply protects both uptime and budget. ESCT Fab Support offers the ES7099-119 inner cover ring as a verified alternative to the OEM part, supporting fabs that want to qualify a second source without compromising performance.
It is a high-purity silicon ring that sits around the wafer in the inner chamber assembly, shielding the underlying hardware from plasma while presenting a process-compatible silicon surface that helps shape the sheath and stabilise the chemistry at the wafer edge.
No. ES7099-119 is supplied as a second-source new part that is OEM-compatible. It is manufactured to match the form, fit and function of OEM P/N 2L10-355557-11 but is not an original Tokyo Electron part and is not sold as one.
The 330.3 figure denotes the ring’s nominal diameter class within the inner cover family, while V2 indicates the second-generation revision of the design, a refined profile or finish introduced to improve uniformity or service life over the original version.
Silicon is chemically compatible with the wafer being processed, so any material sputtered or etched from the ring stays within the silicon family rather than introducing foreign contamination. Silicon also participates usefully in the edge chemistry, helping balance reactive species near the wafer.
Replacement is normally driven by accumulated RF hours and PM schedule, but watch for edge etch-rate or profile drift, rising particle counts, visible thinning of the V2 profile, surface roughening or any cracks and chips. Any of these indicates the ring has reached the end of its useful life.
The typical lead time is 4–5 weeks. We recommend holding the ring as a planned consumable spare and aligning orders with your preventive-maintenance calendar to avoid unplanned downtime.
The Silicon Inner Cover Ring 330.3 (V2), ESCT P/N ES7099-119, is a plasma-facing silicon consumable for TEL 300 mm plasma etch chambers, cross-referenced to OEM P/N 2L10-355557-11. It protects underlying inner-chamber hardware, presents a process-compatible silicon surface to the discharge and helps define the sheath and chemistry at the wafer edge. Because edge uniformity, particle performance and chamber matching all depend on its condition, it is best managed as a scheduled consumable with a qualified second-source supply. ESCT Fab Support provides it as a second-source new part with a typical 4–5 week lead time.
Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Tokyo Electron part number 2L10-355557-11. It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Tokyo Electron, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.
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