CEL,OUTER ST(NEST)V2(POLY)

PART DETAILS

2L10-251343-21
CEL,OUTER ST(NEST)V2(POLY)

OEM P/N: 

2L10-251343-21

ESCT P/N: 

ES7099-124

PART TYPE:

2nd Source NEW

OEM: 

TEL
MORE INFO

CEL outer silicon electrode ring, Poly version 2 (OEM P/N 2L10-251343-21), outer electrode consumable ring for TEL 300 mm plasma etch systems

ESCT P/N ES7099-124, second-source poly-silicon outer cathode electrode ring for Tokyo Electron 300 mm dielectric and conductor etch chambers

The CEL Outer Silicon Electrode Ring (OEM P/N 2L10-251343-21) is an annular consumable electrode component used in Tokyo Electron (TEL) 300 mm plasma etch process chambers. The OEM designation “CEL, OUTER ST(NEST)V2(POLY)” identifies it as the outer member of a Cathode ELectrode (CEL) assembly: a poly-silicon (“POLY”) ring that nests around and circumscribes the central silicon electrode, with “V2” denoting the second-generation profile and “ST(NEST)” referring to its seated, nesting fit into the cathode pocket of the lower electrode stack.

In a TEL capacitively coupled etch chamber, the silicon cathode electrode forms the wafer-bearing plane and the primary RF-driven surface that sustains the plasma. The CEL outer ring sits concentrically outboard of the inner electrode and immediately beneath or surrounding the wafer edge region, bridging the active electrode area to the surrounding insulator and focus-ring stack. Because it is fabricated from poly-silicon rather than a dielectric, it remains part of the electrically active and chemically reactive surface that the plasma sees, making it a true consumable rather than a structural part.

Its position at the transition between the central electrode and the chamber periphery means it directly shapes the electric-field profile, the plasma sheath geometry and the silicon-loading balance at the wafer edge. Even small changes in its thickness, surface condition or seating contact translate into measurable shifts in edge etch rate, profile angle and particle generation, which is precisely why fabs schedule it as a planned-replacement wear part.

Functional role of the CEL outer silicon electrode ring in TEL plasma etch platforms

The outer CEL ring is an active electrode surface, not a passive spacer. As a poly-silicon member nested into the cathode stack, it performs several coupled electrical, chemical and mechanical functions that govern process behaviour at the wafer edge.

  • Extends the active silicon electrode area outboard of the inner electrode, maintaining a continuous, electrically conductive surface across the cathode plane.
  • Carries and distributes RF current at the electrode periphery, providing a defined RF return path and helping to confine the plasma over the cathode rather than letting it spread to chamber walls.
  • Shapes the electric-field and sheath profile at the wafer edge, controlling ion-trajectory angle and edge etch directionality.
  • Contributes silicon to the plasma chemistry, acting as a sacrificial silicon source that buffers fluorine loading and stabilises the etch environment around the wafer perimeter.
  • Provides a precise nesting seat that locates the inner electrode and surrounding focus-ring components concentrically within the cathode pocket.
  • Forms part of the thermal contact path at the electrode edge, influencing how heat is conducted away from the wafer perimeter during high-power etching.

Material and process performance

Poly-silicon material behaviour

The ring is manufactured from poly-silicon, selected because its electrical conductivity and silicon chemistry closely match the requirements of an active cathode electrode surface. Unlike single-crystal silicon, the poly-crystalline structure offers a cost-effective, dimensionally stable body for a peripheral electrode member while still presenting an essentially silicon surface to the plasma.

  • Controlled resistivity to sustain uniform RF coupling and avoid localised current crowding at the electrode edge.
  • Predictable, near-uniform erosion under fluorine- and oxygen-bearing plasmas, giving a repeatable wear signature for end-of-life planning.
  • High silicon purity to limit metallic contamination and protect device yield.
  • Tight thickness and flatness tolerances so the as-installed electrode plane matches the inner electrode and focus-ring datum.

Plasma and erosion resistance

Sitting in the densest part of the discharge at the wafer edge, the ring is subjected to continuous ion bombardment and reactive-radical attack. Its performance is judged by how slowly and how evenly it erodes, because uniform recession preserves field geometry far longer than patchy or accelerated wear.

  • Sputter and chemical erosion gradually thin the exposed surface, slowly lowering the local electrode plane.
  • Surface roughening and micro-pitting accumulate over hundreds of RF hours and seed particle release.
  • Polymer and etch by-product redeposition on cooler zones can flake if not removed during scheduled wet cleans.
  • Sharp original edges round off over time, altering the sheath shape directly above the wafer perimeter.

Impact on tool performance and yield

Because the outer CEL ring defines the electrical and chemical boundary conditions at the wafer edge, its condition has an outsized effect on edge-of-wafer results, exactly the region where process windows are tightest and yield loss concentrates.

  • A worn or recessed ring shifts the edge etch rate, degrading within-wafer uniformity and edge critical dimension control.
  • Changes in sheath geometry tilt ion trajectories, producing profile tilt or notching in the outer die.
  • Disturbed RF coupling can alter plasma confinement and impedance, nudging the match network and overall etch behaviour.
  • Eroded or flaking silicon becomes a particle source, raising defect counts and scrap.
  • Poor seating contact introduces electrode-plane errors and run-to-run drift that consume engineering time to chase.

Common wear and failure modes

Erosion and thickness loss

The dominant end-of-life mechanism is steady sputter and chemical erosion of the plasma-facing surface. As the ring thins, the local electrode plane drops relative to the wafer and inner electrode, gradually pulling edge etch performance outside the qualified window and triggering planned replacement.

Surface roughening and particle generation

Prolonged ion bombardment roughens the poly-silicon and, combined with redeposited polymer, creates loosely adhered material. Once these films or asperities reach a critical state they shed particles onto the wafer, so a rising edge-defect signature is often the practical end-of-life indicator before pure dimensional limits are hit.

Cracking, chipping and seating faults

Silicon is brittle, so thermal cycling, mishandling during a parts change or debris trapped under the nesting seat can cause edge chips or hairline cracks. A ring that does not seat fully sits proud or cocked, producing arcing, localised hot spots and accelerated, uneven erosion that shortens service life dramatically.

Installation and replacement guidance

Replacement is a precision task carried out during scheduled preventive maintenance. Follow TEL-approved procedures, observe ESD precautions and handle the poly-silicon ring only with clean, powder-free gloves to avoid contamination and fracture.

  • Vent and isolate the chamber, lock out RF and gas supplies, and allow the electrode stack to cool fully before opening.
  • Remove the focus-ring and upper consumables in sequence to expose the cathode pocket, recording the build order and orientation.
  • Lift out the worn outer CEL ring, then inspect and clean the cathode seat, removing all polymer, particles and erosion debris from the nesting surface.
  • Verify the new ring against ES7099-124 / 2L10-251343-21 for the correct V2 poly profile and inspect it for chips, cracks or handling marks.
  • Seat the replacement squarely into the nest, confirming full, even contact with no rocking, gap or proud edge.
  • Reassemble the surrounding consumables to the recorded order and torque values, then close the chamber.
  • Pump down, run leak and RF checks, perform a season/conditioning recipe, and requalify edge uniformity before returning to production.

Spare parts strategy for TEL 300 mm etch consumables

Active silicon electrode consumables like the outer CEL ring are consumed on a predictable RF-hour cadence, so availability and lead-time certainty are as important as the part itself. ESCT Fab Support supplies ES7099-124 as a second-source alternative that is verified to the form, fit and function of the original, helping fabs hold the cathode stack to specification without single-source exposure.

  • New second-source poly-silicon ring cross-referenced to TEL OEM P/N 2L10-251343-21 for confident planning.
  • Dimensional and material conformance to the V2 outer-electrode profile to protect edge process performance.
  • A defined 4-5 week lead time that supports structured preventive-maintenance and reorder scheduling.
  • A cost-effective, qualified alternative that reduces dependence on a single OEM supply channel.
  • Clear ESCT and OEM part referencing to simplify stores management and kit building for parts changes.

Frequently asked questions

What does this CEL outer ring actually do in the chamber?

It is the outer member of the cathode silicon electrode assembly. Nested around the inner electrode, it extends the active electrode surface to the wafer edge, carries RF current at the periphery, shapes the plasma sheath and contributes silicon to the etch chemistry, all of which govern edge etch uniformity and particle performance.

Is ES7099-124 an original TEL OEM part?

No. ES7099-124 is supplied as a new, second-source OEM-compatible part cross-referenced to TEL OEM P/N 2L10-251343-21. It is verified to the form, fit and function of the original but is not an original OEM-branded component.

Why is it made from poly-silicon?

Poly-silicon gives the electrical conductivity and silicon surface chemistry an active cathode electrode needs, while offering a dimensionally stable and cost-effective body for a peripheral ring. The “POLY” tag in the part name distinguishes this variant from single-crystal electrode members.

How do I know when it needs replacing?

End of life is usually signalled by drift in edge etch rate or uniformity, rising edge particle and defect counts, or measured thickness loss approaching the recession limit. Most fabs replace it on a planned RF-hour interval rather than waiting for an out-of-spec event.

Does poor seating really matter that much?

Yes. Because the ring is an RF-active electrode surface, a ring that sits proud, cocked or on trapped debris causes uneven field coupling, potential arcing, hot spots and accelerated erosion. Confirming a flat, fully seated nest fit is one of the most important checks during installation.

What is the lead time for this part?

The current lead time is 4-5 weeks. Because it is a planned-replacement consumable, we recommend aligning reorder points with your preventive-maintenance schedule and holding appropriate safety stock to avoid tool downtime.

Summary

The CEL Outer Silicon Electrode Ring (OEM P/N 2L10-251343-21, ESCT P/N ES7099-124) is a poly-silicon V2 outer-electrode consumable for Tokyo Electron 300 mm plasma etch chambers. Nested around the inner cathode electrode, it extends the active electrode plane to the wafer edge, manages RF current and sheath geometry, and contributes silicon to the etch chemistry, making its condition a direct driver of edge uniformity, profile control and particle performance. As a steadily eroding wear part, it is best managed on a planned-replacement basis, and ESCT supplies it as a verified, cost-effective second-source alternative with a defined 4-5 week lead time.

Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Tokyo Electron part number 2L10-251343-21. It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Tokyo Electron, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.

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