CEL,OUTER SS-L V2(POLY)

PART DETAILS

2L10-355755-11
CEL,OUTER SS-L V2(POLY)

OEM P/N: 

2L10-355755-11

ESCT P/N: 

ES7099-127

PART TYPE:

2nd Source NEW

OEM: 

TEL
MORE INFO

Outer silicon electrode ring, SS-L V2 (polysilicon) (OEM P/N 2L10-355755-11), outer CEL ring for TEL 300 mm plasma etch systems

ESCT Fab Support P/N ES7099-127, outer silicon cathode electrode (CEL) ring, second-source new, for Tokyo Electron 300 mm etch chambers

The Outer Silicon Electrode Ring (CEL, OUTER SS-L V2, polysilicon variant) is a consumable plasma-facing ring fitted to the upper or lower electrode assembly of Tokyo Electron (TEL) 300 mm plasma etch process chambers. The designation “CEL” identifies it as a cathode electrode component, part of the family of silicon electrode parts that form the active, plasma-coupled surface of the chamber. The “OUTER” qualifier distinguishes this ring from the central electrode plate it surrounds, and the “(POLY)” suffix confirms the part is manufactured from polycrystalline silicon rather than single-crystal silicon, an important distinction for both its electrical behaviour and its erosion characteristics.

In a capacitively coupled etch chamber, the electrode is the surface through which RF energy is delivered to sustain the plasma. The outer electrode ring occupies the annular region around the main electrode, sitting at the periphery of the active area directly above or below the 300 mm wafer edge. Because it is silicon, it is chemically and electrically compatible with the process: it participates in the plasma chemistry, conducts RF return current, and is consumed slowly by ion bombardment and reactive radicals over the course of many wafer passes. As a sacrificial silicon part, it protects more costly chamber hardware while shaping the field and chemistry at the wafer edge.

Because the outer ring sits precisely where edge effects dominate, its condition has an outsized influence on the uniformity of the last few millimetres of every wafer. As the silicon erodes and its profile changes, etch rate, critical dimension and selectivity at the wafer edge drift, which is why this ring is tracked as a scheduled consumable and replaced on a defined wafer-count or hours interval rather than run to failure.

Functional role of the outer silicon electrode ring in TEL etch platforms

The outer CEL ring performs several overlapping electrical, chemical and mechanical duties at the chamber periphery. It is not a passive spacer; it is an active part of the electrode that directly couples to the plasma and helps define the boundary conditions of the discharge.

  • Completes the active silicon electrode area around the central plate, providing a continuous conductive surface for RF coupling at the wafer edge.
  • Provides an RF return and current path so that sheath voltage and plasma density remain symmetric across the full electrode diameter.
  • Acts as a sacrificial silicon source, consuming reactive species in a controlled way so that fluorine, chlorine or bromine chemistries behave predictably across the edge zone.
  • Shapes the electric field and plasma sheath at the periphery, helping to terminate the active area cleanly and confine the discharge above the wafer.
  • Protects the underlying electrode body, insulators and chamber metalwork from direct ion and radical attack.
  • Maintains a defined, repeatable surface geometry so that edge etch results stay matched from chamber to chamber and across preventive-maintenance cycles.

Material and process performance

As a polysilicon plasma-facing consumable, the behaviour of this ring is governed by silicon purity, grain structure and dimensional precision. The polycrystalline grade is selected for cost-effective, uniform erosion and for predictable electrical contribution to the discharge.

Silicon grade and erosion behaviour

High-purity polysilicon erodes through physical sputtering and chemical reaction with the plasma. A controlled grain structure and low impurity content keep the etch-back of the ring surface even, avoiding localised pitting that would create micro-masking or particle sources. Because polysilicon presents many grain boundaries rather than a single lattice, its erosion signature differs subtly from single-crystal parts, which is why the polysilicon variant should not be substituted with a monocrystalline ring without process re-qualification.

  • High-purity polysilicon minimises metallic contamination transfer to the wafer edge.
  • Uniform grain structure promotes smooth, predictable surface recession over the ring’s service life.
  • Controlled resistivity keeps RF coupling consistent as the part ages.
  • Stable response to fluorine- and chlorine-based chemistries used in dielectric, poly and conductor etch.

Dimensional precision and surface finish

The seating geometry, flatness and concentricity of the ring determine how it mates to the electrode body and how it presents to the plasma. Out-of-tolerance flatness creates gaps that disturb RF return and thermal contact, while a poor surface finish raises early particle counts. The SS-L V2 revision reflects the OEM’s dimensional and surface specification, and this second-source ring is manufactured to match that form, fit and function.

  • Tight flatness and concentricity give repeatable seating against the electrode.
  • Specified surface finish reduces particle generation during early wafer passes.
  • Consistent ring height preserves the intended sheath and gap geometry at the edge.
  • Clean, contaminant-free machining supports a fast return to process after replacement.

Impact on tool performance and yield

Because the outer electrode ring sits at the wafer edge, the zone where uniformity is hardest to control, its condition feeds directly into device yield, particularly for the outermost die. A worn, cracked or out-of-spec ring shifts edge results in ways that are visible on radial uniformity maps long before the part fails outright.

  • Edge-to-centre etch rate and critical-dimension uniformity, which determine yield on perimeter die.
  • Plasma symmetry and stability, affecting run-to-run and chamber-to-chamber matching.
  • Particle and defect counts, since an eroded or cracked silicon surface becomes a contamination source.
  • RF stability and impedance, influencing power coupling and reflected-power behaviour.
  • Mean time between cleans and preventive-maintenance frequency, driving tool availability and cost of ownership.

Common wear and failure modes

Plasma erosion and surface recession

The primary wear mechanism is gradual etch-back of the silicon by ion bombardment and reactive radicals. As the ring thins and its profile changes, the sheath geometry and field shaping at the edge drift, pushing edge etch rate and critical dimension out of specification. This is an expected, progressive process, which is why the ring is replaced on a planned interval before recession becomes large enough to affect yield.

Cracking and thermal stress

Silicon is brittle, and repeated thermal cycling, mechanical clamping stress or mishandling during a preventive-maintenance event can initiate cracks or chips, often at the seating face or an edge. Polysilicon grain boundaries can act as crack-propagation paths. A fractured ring disturbs RF return, can arc, and sheds silicon particles onto the wafer, so any visible crack is cause for immediate replacement.

Polymer build-up and contamination

Etch by-products and polymer films accumulate on and around the ring between cleans. Flaking deposits become particle defects, while uneven build-up changes the local surface condition and can mask the silicon, altering its chemical contribution to the plasma. Heavy or baked-on residue, surface discolouration and roughening at the end of a clean cycle all signal that the ring should be inspected and, where outside specification, replaced.

Installation and replacement guidance

Replacement should follow the TEL maintenance procedure for the specific platform and be performed by trained technicians under proper contamination controls. The following sequence summarises good practice for a silicon electrode ring change.

  • Vent the chamber, isolate RF and gas, and follow lock-out/tag-out before opening the lid or electrode assembly.
  • Remove the worn outer ring carefully, noting its orientation and recording wafer count or hours in service for trend records.
  • Inspect and clean the electrode seating surface, removing polymer residue and confirming there are no burrs, particles or damage to the mating face.
  • Unpack the new ring in a clean environment and handle it with powder-free gloves only, avoiding contact with the plasma-facing surface.
  • Seat the new ring squarely so it sits flat and concentric, checking that there are no gaps that would compromise RF return or thermal contact.
  • Reassemble the electrode and chamber, pump down and run the prescribed leak check, season or burn-in recipe to condition the new silicon surface.
  • Verify edge uniformity and particle performance on monitor wafers before returning the chamber to production.

Spare parts strategy for TEL etch consumables

Silicon electrode rings are recurring consumables, so sourcing strategy has a direct effect on cost of ownership and tool availability. ESCT Fab Support supplies this outer CEL ring as a second-source new part built to match the OEM specification, giving fabs a qualified alternative to single-source OEM procurement.

  • Verified to the form, fit and function of OEM P/N 2L10-355755-11 for direct fitment.
  • Cross-referenced under ESCT P/N ES7099-127 for straightforward ordering and inventory control.
  • Second-source supply reduces dependence on a single OEM channel and supports competitive pricing.
  • Manufactured from high-purity polysilicon to preserve etch and particle performance.
  • Typical lead time of 4–5 weeks supports planned preventive-maintenance scheduling and buffer stocking.
  • Backed by ESCT technical support for fitment and application questions.

Frequently asked questions

What does this part do in the chamber?

It is the outer silicon electrode (CEL) ring that surrounds the central electrode in a TEL 300 mm plasma etch chamber. It completes the active silicon electrode surface, carries RF return current, shapes the plasma sheath at the wafer edge and acts as a sacrificial silicon source, directly influencing edge etch uniformity and particle performance.

Is this an original OEM part?

No. This is a second-source new part, supplied as an OEM-compatible component verified to the form, fit and function of TEL OEM P/N 2L10-355755-11. It is not an original Tokyo Electron part and is not sold as one; it is offered as a qualified alternative for fabs seeking a competitive second source.

Why does the “(POLY)” designation matter?

The “(POLY)” suffix confirms the ring is made from polycrystalline silicon rather than single-crystal silicon. Polysilicon has a different grain structure that affects erosion behaviour and electrical contribution, so a polysilicon ring should not be interchanged with a monocrystalline variant without process re-qualification.

How often should the ring be replaced?

Replacement is driven by accumulated wafer count, RF hours or measured drift in edge uniformity and particle data rather than a fixed calendar period. Each fab sets its own preventive-maintenance interval from its process intensity and yield requirements; the ring is treated as a scheduled consumable and replaced before erosion affects results.

What is the typical lead time?

The typical lead time for this ring is 4–5 weeks. Because it is a recurring consumable, we recommend planning orders against preventive-maintenance schedules and holding appropriate buffer stock to avoid unplanned tool downtime.

How should the ring be handled and stored?

Silicon is brittle and contamination-sensitive, so the ring should be kept in its original clean packaging until use, handled only with powder-free gloves and never set down on the plasma-facing surface. Avoid mechanical shock and keep it dry and dust-free; mishandling is a common cause of chips and cracks that lead to early failure.

Summary

The Outer Silicon Electrode Ring, SS-L V2 polysilicon (OEM P/N 2L10-355755-11, ESCT P/N ES7099-127), is a plasma-facing consumable for TEL 300 mm etch chambers that completes the silicon electrode at the wafer edge, carries RF return current, shapes the peripheral plasma sheath and serves as a controlled sacrificial silicon source. Its condition has a direct bearing on edge uniformity, particle counts, RF stability and ultimately yield on perimeter die. Supplied by ESCT Fab Support as a second-source new part built to match the OEM specification, with a typical 4–5 week lead time, it gives fabs a qualified, cost-effective option for keeping their TEL etch chambers in specification.

Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Tokyo Electron part number 2L10-355755-11. It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Tokyo Electron, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.

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