3D10-202364-12
(C2)SILICON CEL INNER(TE-T10-P-LABY)

Silicon CEL inner electrode, labyrinth type (OEM P/N 3D10-202364-12), inner confinement electrode ring for TEL 300 mm plasma etch systems

ESCT P/N ES7099-009 · Tokyo Electron (TEL) compatible silicon cathode component · 2nd-source new

The Silicon CEL Inner Electrode is a high-purity silicon consumable that sits within the upper electrode assembly of Tokyo Electron (TEL) 300 mm plasma etch process chambers. In TEL nomenclature, “CEL” denotes the confinement electrode group that surrounds and supports the main silicon electrode plate, and this particular component is the inner member of that group, the “C2” designation and the “TE-T10-P-LABY” reference both point to a labyrinth-profile inner ring carried on the cathode (upper electrode) side of the chamber. The labyrinth geometry is the defining feature: rather than a flat interface, the part presents a stepped, interlocking edge that mates with the adjacent confinement parts to form a tortuous gas path.

Manufactured from semiconductor-grade silicon, the inner electrode is sacrificial by design. It is positioned directly at the boundary of the active plasma, where it shares the same RF potential and chemical environment as the main electrode while shielding the structural metalwork behind it from ion bombardment and fluorine-based chemistries. As a silicon part in a silicon-etch or dielectric-etch environment, it is chosen specifically because its erosion products are chemically benign relative to metal or quartz alternatives, helping keep the wafer environment clean.

Because it governs both the local electric field at the chamber edge and the conductance of process gas leaving the confinement region, the Silicon CEL Inner Electrode has a direct bearing on plasma confinement, edge etch uniformity and particle performance. It is a routinely replaced wear part, and maintaining a verified supply of correctly profiled inner electrodes keeps a fleet of TEL etch chambers matched and productive.

Functional role of the silicon CEL inner electrode in TEL plasma etch platforms

Within the upper electrode stack, the inner CEL electrode performs several interlocking jobs that together stabilise the plasma over the wafer and protect the chamber hardware. Its silicon construction and labyrinth profile are both deliberate, and each contributes to a specific process function:

• Defining the inner boundary of the plasma confinement region so the discharge stays located over the wafer rather than spreading into chamber recesses.
• Carrying RF potential as part of the cathode assembly and shaping the electric field near the wafer edge, which sets edge ion energy and direction.
• Forming, through its labyrinth step, a controlled-conductance gas path that lets neutrals and by-products exit while resisting plasma leakage and arcing across the gap.
• Presenting a sacrificial silicon surface to fluorine and oxygen radicals, so that erosion consumes the consumable rather than the underlying electrode body or metal hardware.
• Contributing silicon-based etch chemistry into the discharge in a clean, predictable way, helping to scavenge fluorine and tune the etch regime near the wafer perimeter.
• Acting as a particle barrier that keeps redeposited films and flakes away from the wafer surface during the process step.

Material and process performance

Silicon purity and erosion behaviour

The performance of any CEL electrode begins with the silicon itself. High-purity, controlled-resistivity silicon is used so that the part presents a predictable electrical character to the RF circuit and so that its erosion products do not introduce metallic contamination onto the wafer. As the surface is exposed to energetic ions and fluorine radicals it erodes uniformly rather than spalling, and the rate of that erosion is one of the key inputs to the chamber’s preventive-maintenance interval.

• Semiconductor-grade silicon with low metallic impurity content to protect wafer cleanliness.
• Controlled resistivity for a consistent, repeatable RF and field response.
• Uniform, predictable erosion that supports stable process drift and scheduled replacement.
• Chemically compatible erosion products that suit silicon and dielectric etch chemistries.

Labyrinth geometry and dimensional fidelity

The labyrinth profile is what distinguishes this inner electrode from a plain ring, and it only works if the part is machined to tight tolerances. The stepped edge must mate precisely with the surrounding confinement components to set the correct gap conductance and to keep the plasma sheath anchored at the intended boundary. Surface finish, step depth and concentricity all influence how the gas path behaves and how evenly the field is presented around the full circumference.

• Precise labyrinth step depth and width to set the designed gas conductance and arc resistance.
• Tight concentricity and flatness for azimuthally even confinement and field shaping.
• Controlled surface finish to minimise particle generation and local field enhancement.
• Mating-face accuracy so the inner electrode seats correctly against adjacent CEL parts.

Impact on tool performance and yield

Although it is a relatively small component, the inner CEL electrode influences several of the metrics that fab process engineers watch most closely. A worn, mismatched or incorrectly profiled part propagates straight into wafer results:

• Edge etch-rate uniformity and critical-dimension control across the outer wafer zones.
• Plasma confinement stability, which affects centre-to-edge symmetry of the discharge.
• Particle counts and on-wafer defectivity as the silicon surface erodes or flakes.
• RF return-path consistency and resistance to arcing at the confinement gap.
• Chamber-to-chamber matching across a fleet of TEL etch tools running the same recipe.
• Mean time between cleans and the stability of process drift over a maintenance cycle.

Common wear and failure modes

Plasma erosion and thinning

The dominant wear mechanism is steady erosion of the silicon surface by ion bombardment and fluorine attack. Over time the labyrinth step rounds off and the part thins, which opens up the confinement gap, alters gas conductance and shifts the edge field. Beyond a certain point the erosion changes the etch profile at the wafer perimeter and the electrode must be replaced to recover the original process window.

Arcing, cracking and thermal stress

Silicon is brittle, and the inner electrode is exposed to repeated thermal cycling and intense RF fields. Localised arcing at the labyrinth gap, a contaminated mating face or a handling-induced micro-crack can all seed a fracture. A cracked electrode generates particles, distorts the local field and can fail abruptly, so any chipping, hairline cracking or arc-burn marks seen at a PM are grounds for immediate replacement.

Deposition build-up and particle shedding

Process by-products redeposit on the cooler and recessed faces of the labyrinth. As these films thicken they stress, crack and shed flakes that raise particle counts and on-wafer defects. Build-up in the labyrinth channel also degrades the gas path and can promote arcing, which is why deposition state is assessed alongside raw erosion when deciding whether to replace the part.

Installation and replacement guidance

Replacement is normally carried out during a scheduled preventive-maintenance window with the chamber vented and the upper electrode assembly accessible. Always follow the applicable TEL maintenance procedure and your site’s safety rules; the steps below summarise good practice for a silicon confinement consumable:

• Place the tool in maintenance mode, vent the chamber and confirm RF and gas systems are isolated and safe to work on.
• Gain access to the upper electrode assembly and note the orientation and seating of the existing inner CEL electrode before removal.
• Remove the worn electrode carefully, supporting the brittle silicon to avoid chipping, and inspect adjacent confinement parts and mating faces for wear or deposition.
• Clean the mating surfaces per procedure and verify the new ES7099-009 part is free of cracks, chips and contamination, handling it only with clean, powder-free gloves.
• Seat the new inner electrode in the correct orientation, so the labyrinth step engages fully and evenly with the surrounding CEL components.
• Reassemble the upper electrode stack to the specified torque sequence, then close, pump down and leak-check the chamber.
• Run the prescribed season or burn-in recipe and verify edge uniformity, particle counts and RF stability before returning the chamber to production.

Spare parts strategy for TEL plasma etch chambers

Silicon confinement electrodes are consumed on a predictable cadence, so holding verified replacements on the shelf is a core part of any TEL etch fleet’s uptime plan. ESCT Fab Support supplies the Silicon CEL Inner Electrode as a cost-effective, fit-for-purpose alternative to sole-sourcing through the OEM, with the following advantages:

• A 2nd-source new part verified to the original form, fit and function of OEM P/N 3D10-202364-12.
• Referenced under ESCT P/N ES7099-009 for clean cross-checking against your internal catalogue.
• Competitive pricing that reduces the cost of a high-turnover consumable across a fleet.
• A typical lead time of 4–5 weeks to support planned PM scheduling and stock replenishment.
• Suitability for safety-stock and kitting strategies that protect chamber availability.
• Knowledgeable support for identifying the correct confinement consumables for your chamber configuration.

Frequently asked questions

What does the silicon CEL inner electrode actually do?

It is the inner member of the confinement electrode (CEL) group within the upper electrode assembly of a TEL 300 mm plasma etch chamber. It defines the inner boundary of the plasma confinement region, carries RF potential to help shape the field at the wafer edge, and its labyrinth step forms a controlled gas path while presenting a sacrificial silicon surface to the plasma.

Is this an original TEL OEM part?

No. This is supplied as a 2nd-source new part that is verified to the form, fit and function of TEL OEM P/N 3D10-202364-12. It is not an original OEM-branded component, but it is a new, unused part intended as a compatible replacement for that electrode.

What material is it made from?

It is machined from high-purity, controlled-resistivity semiconductor-grade silicon. This material is chosen so the part presents a predictable electrical character to the RF circuit and so that its erosion products remain chemically compatible with silicon and dielectric etch chemistries, protecting wafer cleanliness.

How do I know when it needs replacing?

Replacement is driven by erosion of the silicon and the labyrinth step, by deposition build-up in the gas path, and by any visible cracking, chipping or arc damage found at a PM. As wear opens the confinement gap, you may also see drift in edge uniformity, rising particle counts or RF instability, all of which signal that the electrode has reached the end of its useful life.

Why does the labyrinth geometry matter?

The stepped labyrinth forms a tortuous, controlled-conductance gas path that lets neutrals and by-products exit the confinement region while resisting plasma leakage and arcing across the gap. Because it depends on a precise mate with the surrounding CEL parts, the step depth, concentricity and surface finish must be machined to tight tolerances to reproduce the original confinement and gas-flow behaviour.

What is the lead time and reference number?

The part carries ESCT P/N ES7099-009 and corresponds to TEL OEM P/N 3D10-202364-12. Typical lead time is 4–5 weeks, which makes it well suited to planned preventive-maintenance scheduling and safety-stock replenishment rather than emergency-only sourcing.

Summary

The Silicon CEL Inner Electrode (TEL OEM P/N 3D10-202364-12, ESCT P/N ES7099-009) is the inner labyrinth-profile confinement electrode in the upper electrode assembly of TEL 300 mm plasma etch chambers. Made from high-purity silicon, it defines the inner edge of the plasma confinement region, helps shape the RF field at the wafer perimeter, forms a controlled gas-conductance path through its labyrinth step and presents a clean sacrificial surface to the plasma. As a consumable subject to erosion, arcing and deposition, it is replaced on a regular PM cadence, and a reliable supply directly supports edge uniformity, particle performance and chamber matching across an etch fleet.

Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Tokyo Electron part number 3D10-202364-12. It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Tokyo Electron, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.

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