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The Outer CEL Silicon Electrode Ring is an annular consumable that surrounds the central cathode electrode (CEL) within Tokyo Electron (TEL) 300 mm plasma etch process chambers. Identified in the OEM nomenclature as “(C2)CEL, OUTER (TE-349-LABY-GND FLAT)”, this is the outer member of a multi-part silicon electrode assembly, distinguished by its integral labyrinth interface and a machined ground flat that fixes its rotational orientation relative to the cathode stack. It sits at the periphery of the powered electrode, completing the silicon surface that the plasma sees directly above the wafer edge.
In a capacitively coupled etch chamber, the silicon electrode is not merely a structural part; it is an electrically active, plasma-facing surface that participates in the discharge. The outer ring extends the conductive silicon plane outward from the wafer perimeter, shaping the sheath at the most yield-critical region of the substrate. Because it is a silicon part exposed to fluorine- and chlorine-based chemistries and continuous ion bombardment, it is consumed over time and is treated as a scheduled replacement consumable rather than a permanent assembly.
The labyrinth feature provides a tortuous gas and plasma path at the joint between the outer ring and the adjacent electrode members, suppressing parasitic discharge and limiting deposition or etchant ingress into the interface. The ground flat keys the part to a single correct orientation, so the labyrinth registers precisely and the RF and ground return geometry is repeatable from one rebuild to the next. ESCT Fab Support supplies this component under ES7099-010 as a 2nd source, brand-new part verified to the form, fit and function of TEL OEM P/N 3D10-202375-21.
The outer CEL ring completes the silicon electrode surface around the wafer edge and manages the electrical and gas-path transitions between the powered electrode and the surrounding grounded hardware. Its functions in the chamber include the following.
CEL electrode rings are manufactured from high-purity silicon selected for controlled resistivity and low trace-metal content. Because the part is both a plasma-facing surface and an electrically active electrode, its silicon grade governs how it couples RF power, how cleanly it erodes, and how little metallic or particulate contamination it sheds into the process.
The performance of an outer CEL ring depends as much on its machined geometry as on its material. The labyrinth gap and the ground flat must be held to tight tolerance so that the part registers correctly against the adjacent electrode members and reproduces the intended electrical and gas-confinement behaviour.
As an edge-region, plasma-facing electrode part, the outer CEL ring has a direct and measurable influence on etch results and on the defectivity recorded at the wafer perimeter. Its condition propagates into several yield-relevant outcomes.
Continuous ion bombardment and fluorine attack gradually erode the silicon surface, thinning the ring and rounding its features. As material is lost the sheath geometry shifts, edge etch rate drifts and the labyrinth clearance opens up, eventually allowing parasitic discharge that would not occur on a fresh part.
Silicon is brittle, and repeated thermal cycling combined with mechanical handling can initiate micro-cracks, chips or full fracture, often at the ground flat or other geometric transitions. A cracked ring sheds silicon particles into the chamber, driving edge defectivity and risking damage to the wafer and adjacent hardware.
Polymer build-up, etchant ingress or a poorly seated joint can compromise the ground and RF return path. The result is localised arcing at the electrode interface, which scars the silicon, destabilises the plasma and accelerates wear. Misorientation that defeats the ground flat keying produces the same symptoms.
Replacing the outer CEL ring should follow TEL-approved procedures for the specific platform, performed by trained technicians under proper contamination controls. The following sequence outlines good practice.
Silicon electrode rings are scheduled consumables, so a reliable second source protects both uptime and budget. ESCT Fab Support offers ES7099-010 as a qualified alternative to the OEM part with practical advantages for fab maintenance planning.
It is the outer silicon member of the cathode electrode (CEL) assembly. It extends the powered silicon surface around the wafer edge, shapes the plasma sheath at the chamber periphery, manages the ground and RF return path, and serves as a sacrificial surface that erodes in place of more costly central hardware.
No. ES7099-010 is supplied as a 2nd source, brand-new part that is fully compatible with TEL OEM P/N 3D10-202375-21 and verified to its form, fit and function. It is not an original OEM part and is offered as a qualified alternative.
The labyrinth creates a tortuous path at the joint with the adjacent electrode members, suppressing parasitic discharge and limiting gas and deposition ingress. The ground flat keys the ring to one correct orientation so the labyrinth and the RF return geometry register the same way on every rebuild.
Life depends on chemistry, power and duty cycle, so it is governed by each fab’s preventive-maintenance data rather than a fixed interval. Indicators for replacement include measurable thinning, edge etch drift, rising particle counts or any visible cracking or arcing damage.
The standard lead time is 4-5 weeks. Because this is a recurring consumable, we recommend aligning orders with your maintenance schedule and holding appropriate safety stock to avoid unplanned downtime.
Silicon is brittle and contamination-sensitive, so keep the ring in its packaging until use, handle it with powder-free gloves by approved surfaces only, and avoid mechanical shock. Store it clean, dry and supported so the ground flat and edges are not chipped before installation.
The Outer CEL Silicon Electrode Ring (TEL OEM P/N 3D10-202375-21, ESCT P/N ES7099-010) is the outer silicon member of the cathode electrode assembly in TEL 300 mm plasma etch chambers. Through its high-purity silicon surface, precisely machined labyrinth and keyed ground flat, it governs edge etch uniformity, plasma confinement, RF return integrity and particle performance at the wafer perimeter. As a brand-new, qualified 2nd source consumable with a defined 4-5 week lead time, it offers fabs a cost-effective, fit-verified alternative for keeping etch tools matched and in production.
Disclaimer: This part is supplied by ESCT Fab Support as a new, OEM-compatible second-source component, verified to the form, fit and function of Tokyo Electron part number 3D10-202375-21. It is not an original OEM part and is not sold as one. It is not manufactured by, endorsed by, or affiliated with Tokyo Electron, and all manufacturer names and part numbers are quoted for identification and compatibility purposes only.
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